Silicon-on-insulator (SOI) substrates often include a SOI layer over a buried insulator. When the insulator is an oxide, it is also referred to as a buried oxide or BOX. SOI substrates provide an advantage for high speed and low power applications because of the low parasitic capacitance.
As complementary metal oxide semiconductor (CMOS) technology enters the sub-50 nanometer (nm) range, the silicon channel and the buried oxide thicknesses must be less than 50 nm and 100 nm, respectively, in order to prevent the short channel effect (SCE). These requirements, however, present manufacturing problems such as control of Si-SOI layer thickness to within a few percent, precise film electrical properties, and interface characteristics.
Therefore, improved production tools are needed for integrating SOI technology into scaled CMOS devices would be desirable.